1. Field of Invention
The present invention relates to a fabrication method for a multilevel metal interconnects in a semiconductor device. More particularly, the present invention relates to a fabrication method for a dual damascene structure.
2. Description of Related Art
In the development of the semiconductor industry, a goal of a high operational speed for electronic devices is actively pursued by all semiconductor manufacturers and customers. The factors such as the resistance of conductive lines and the formation of parasitic capacitance caused by unnecessary capacitive coupling between the adjacent conductive wires are decisive for the operational speed of devices. A metal with a low resistance for the decrease of resistance and a dielectric material with a low dielectric constant for the improvement of the issue of parasitic capacitance have been chosen for use in the manufacturing of semiconductor devices.
The typical metallic interconnect manufacturing process includes forming a metal plug in the dielectric layer. The second aluminum layer of the metal-interconnect structure is electrically connected to the base layer of metal-interconnect structure via the metal plug formed in the dielectric layer. The dual damascene technique includes a metallic interconnect technique with high reliability and low cost, and the metallic interconnect materials are protected from, etching. The dual damascene technique has been widely applied in the manufacturing of copper line to reduce the resistance of conductive lines, and further improve the operational speed and quality of an integrated circuit. In order to accommodate the demand for high operational speed, dielectric layers with a low dielectric constant have been employed in manufacturing dual damascene structures, which have gradually become the metallic interconnect technique in the semiconductor industry.
FIGS. 1A to 1E are schematic, cross-sectional views showing the dual damascene manufacturing process according to the prior art.
Referring to FIG. 1A, a dielectric layer 102 is formed on a substrate 100, followed by forming a silicon nitride layer 104 to cover the dielectric layer 102. A patterned photoresist 106 with a via opening pattern 108 is further formed to cover the silicon nitride layer 104.
Referring to FIG. 1B, the silicon nitride layer 104 is etched with the photoresist layer 106 serving as a mask to transfer the via opening pattern 108 of the photoresist layer 106 to the silicon nitride layer 104. Thus a via opening 110 is formed in the silicon nitride layer 104. Another inter-metal dielectric layer 112 is formed over the substrate 100 and then a patterned photoresist layer 114 with a trench line pattern 116 is formed over the inter-metal dielectric layer 112.
Referring to FIG. 1C, the portion of the inter-metal dielectric layer 112 uncovered by the patterned photoresist 114 is etched to form a trench line 120. After exposure of the portion of the silicon nitride layer 104 with a via opening 110, etching is further conducted on the exposed dielectric layer 102 under the via opening 110 to form a via 118 in the dielectric layer 102.
Continuing to FIG. 1D and FIG. 1E, the photoresist layer 114 is removed by ashing using O.sub.2 plasma. A metal layer 122 is formed on the substrate 100 and fills the trench 120 and the via 118. Portions of the metal layer 122 which are covering the surface of the dielectric layer 112 are removed by, for example, chemical mechanical polishing (CMP), leaving the metal layer 122 in the trench 120 and in the via 118. At this point, the manufacturing of a dual damascene structure is completed.
As the integration of the devices increases, the density of wires used to electrically couple the transistors or other devices is increased. The issues of parasitic capacitance between the adjacent conductive wires becomes serious. Therefore, at the stage of deep submicron manufacturing, the dielectric constant of the IMD layer is lowered to reduce the parasitic capacitance and therefore to decrease the resistance-capacitance (RC) time delay when electronic signals are being transmitted between the metal lines.
However, the photoresist layer usually contains polymer material while a dielectric material having a low dielectric constant, such as organic polymer, is commonly used. According to the above manufacturing process, during the process of removing the photoresist layer 114 by ashing using oxygen plasma, the organic dielectric material 112 and 102 with a low dielectric constant will be damaged by oxygen plasma. Therefore, moisture is adsorbed on the sidewalls of the trench line 120 and the via opening 118, respectively formed in the organic dielectric material 112 and 102 with a low dielectric constant. As shown in FIG. 1D, moisture is adsorbed on the sidewalls labeled 124 and 126. In the subsequent thermal process, the adsorbed moisture escapes from the sidewalls of the trench line 120 and the via 118, so that the performance when filling the via 118 and the trench 120 with the metal layer 122 is poor due to the adsorbed moisture, resulting in a poisoned via and trench effect.
In addition, according to the prior art, the trench line 120 and via 118 are formed by performing anisotropic etching with the silicon nitride layer 104 serving as an etch-stop layer and as an etching mask, respectively. However, the silicon nitride layer 104 has a dielectric constant of about 7. Effects, such as the increase of the RC delay time contributed by the generation of the parasitic capacitance between the adjacent conductive wires become serious. As a result, the operational speed of a highly integrated circuit is limited.